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Openings for RTL Design Engineers for 5G NR design and development at IIT Hyderabad
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| Posted 6 months ago
Job Description
Openings for RTL Design Engineers for 5G NR design and development at IIT Hyderabad .Please use Link to Apply Button to Apply:
Openings for RTL Design Engineers for 5G NR design and development.
Location: IIT Hyderabad, Sangareddy, Telangana
Responsibilities:
- Architecture exploration and Micro-architecture development
- RTL design and integration for 5G NR UE systems using Verilog/System Verilog
- Collaboration with multi-discipline teams to integrate, test and debug the designs on FPGAs
Required Qualifications:
- Master's/Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent practical experience
- 2 to 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture
Skills/Experience Required
- Strong Domain Knowledge on RTL Design, implementation, and integration for FPGA based designs.
- Experience with RTL coding using Verilog/System Verilog.
- Proficiency in complete FPGA design flow.
- Experience with protocols like AXI4-stream and AXI4.
- Exposure in scripting (Python/TCL).
- Strong debugging capabilities at RTL simulation and FPGA Emulation.
- Proficiency in version control tools like GIT.
Preferred Experience
- Experience with Intel or Xilinx FPGAs especially MPSoC FPGAs
- Experience in Fixed-point arithmetic implementation in Verilog
- Experience with High speed serial communication IPs on FPGAs
- Experience in implementing DSP algorithms
- RTL Development for wireless communication systems (Most preferably 5G NR)
