Job Description

Nvidia's STA team is looking for young engineers (2 years of exp),
NVIDIA Hiring Event - ASIC Engineer Timing Closure / STA
We are now looking for a ASIC Design Engineer - Hardware. As a member of our ASIC backend/timing team, you'll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows. 
You'll be focusing specifically on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip  timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.), design optimization, and gate-level design of high-speed logic.

In this role you will also interface with architecture, RTL design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis/closure all the way from micro-architecture to tape-out.

What you'll be doing:

• Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
• Chip level Integration, physically partitioning and floor planning.
• Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
• Design optimization and timing convergence related tasks.
• Development of PD work flows.

What we need to see:

• BS or MS in Electrical Engineering or Computer Science, or equivalent experience.
• 2+ years of relevant ASIC design experience ideally with a focus in timing.
• Good problem-solving skills and ability to work with cross functional teams solving tough physical design problems is essential.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you! 
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As a part of our recruitment process, you are invited to participate in an online HackerRank test which will be scheduled for Saturday, 23rd November 2024 (more details will be shared by Thursday 21st November EOD).

Technical test will be largely based on Digital fundamentals, Problem Solving & VLSI concepts

We would like to inform you that we will be using proctoring software to monitor for any unusual behavior or activity during the test. Please follow any setup instructions provided to ensure your testing environment is secure. Just to remind you that this is an individual assessment. Refrain from discussing the test questions or answers with anyone else during or after the test. Sharing information can lead to disqualification.