Job Description

QTIMinds Pvt Ltd hiring for Verification Roles
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Requirement 1 :
JD :
Lead AMS IP/chip verification, including reviewing design specifications and defining and executing a verification plan to ensure compliance with specifications.
* Architect, implement, and automate analog, digital, and AMS test benches to verify pre-silicon designs.
* Build System Verilog real number analog behavioral models, monitors, and checkers for DMS/AMS design.
* Work closely with analog, digital, and system designers to verify the implementation meets system requirements.
* Collaborate with digital design verification engineers to architect and implement tests to verify analog/digital interfaces.
* Lead the development of AMS simulation and verification methodologies.
Minimum Qualifications:
* 2-4 years of AMS design verification experience.
* Fluent in System Verilog and real number modeling.
* Experience with Cadence Spectre and AMS simulator.
* Proven understanding of analog IPs, including Bandgap, oscillator, ADC/DAC, LDO, PLL, and Serdes.
* Proficient with a scripting language, such as Python, Tcl, or Perl is mandatory. Preferred Qualifications:
* Experience in developing verification methodology, flows, and automation.
* Experience with AMS chip bring-up and debug.
* Analog/Mixed Signal Circuit verification experience with tape out experience in several of the following: LDO, DC-DC converters, Bandgap, A/D and D/A conversion, Tempsensor, PLLs, etc.
* Good understanding of CMOS and VLSI technologies (device physics, layout effects, sub-micron effects, and device reliability).
Location : Bangalore

Requirement 2 :
JD :
Experience Level: 2-4 years
Develop and execute verification plans for complex digital RTL. Utilize the latest verification tools and methodologies, including UVM (Universal Verification Methodology), SystemVerilog, and formal verification techniques.
Create and maintain testbenches, test cases, and verification environments.
Create and automate regression flow. Perform functional coverage analysis and ensure comprehensive verification coverage.
Debug and resolve design and verification issues in collaboration with design engineers.
Participate in code reviews and provide feedback to improve design quality. Document verification processes, results, and methodologies.
Requirements: Minimum of 4 years of experience in digital RTL verification. Proficiency in SystemVerilog, UVM, and other verification methodologies.
Experience with industry-standard verification tools such as Cadence, Synopsys, or Mentor Graphics.
Strong understanding of digital design principles and RTL coding.
Excellent problem-solving and debugging skills. Ability to work effectively in a team environment and communicate clearly with cross-functional teams.
Knowledge in I2C/I3C, working with Analog team (developing Analog models), EEPROM interface, Interrupt Controller is a plus Knowledge of scripting languages (e.g., Python, Perl) is a plus.
Preferred Qualifications: Experience with formal verification techniques. Knowledge of low-power design and verification techniques.
Location : Bangalore